{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,11,3]],"date-time":"2024-11-03T04:03:05Z","timestamp":1730606585401,"version":"3.28.0"},"reference-count":76,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"11","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2024,11,1]]},"DOI":"10.1587\/transinf.2024edp7019","type":"journal-article","created":{"date-parts":[[2024,7,10]],"date-time":"2024-07-10T22:12:07Z","timestamp":1720649527000},"page":"1408-1421","source":"Crossref","is-referenced-by-count":0,"title":["Runtime Tests for Memory Error Handlers of In-Memory Key Value Stores Using MemFI"],"prefix":"10.1587","volume":"E107.D","author":[{"given":"Naoya","family":"NEZU","sequence":"first","affiliation":[{"name":"Tokyo University of Agriculture and Technology (TUAT)"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroshi","family":"YAMADA","sequence":"additional","affiliation":[{"name":"Tokyo University of Agriculture and Technology (TUAT)"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] B. Schroeder, E. Pinheiro, and W.-D. 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Security Symposium (USENIX Security '16), pp.345-362, 2016."}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E107.D\/11\/E107.D_2024EDP7019\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,2]],"date-time":"2024-11-02T03:43:45Z","timestamp":1730519025000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E107.D\/11\/E107.D_2024EDP7019\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,11,1]]},"references-count":76,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2024edp7019","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"type":"print","value":"0916-8532"},{"type":"electronic","value":"1745-1361"}],"subject":[],"published":{"date-parts":[[2024,11,1]]},"article-number":"2024EDP7019"}}