{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T09:24:51Z","timestamp":1775467491385,"version":"3.50.1"},"reference-count":17,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. &amp; Syst."],"published-print":{"date-parts":[[2024,12,1]]},"DOI":"10.1587\/transinf.2024edp7033","type":"journal-article","created":{"date-parts":[[2024,8,6]],"date-time":"2024-08-06T22:11:39Z","timestamp":1722982299000},"page":"1476-1483","source":"Crossref","is-referenced-by-count":1,"title":["Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic"],"prefix":"10.1587","volume":"E107.D","author":[{"given":"Souhei","family":"TAKAGI","sequence":"first","affiliation":[{"name":"Department of Information &amp; Computer Science, Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takuya","family":"KOJIMA","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, The University of Tokyo"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideharu","family":"AMANO","sequence":"additional","affiliation":[{"name":"Department of Information &amp; Computer Science, Keio University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Morihiro","family":"KUGA","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Electrical Engineering, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masahiro","family":"IIDA","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Electrical Engineering, Kumamoto University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","unstructured":"[1] M. Amagasaki, R. Araki, M. Iida, and T. Sueyoshi, \u201cSLM: A scalable logic module architecture with less configuration memory,\u201d IEICE Trans. Fundamentals, vol.99, no.12, pp.2500-2506, 2016. 10.1587\/transfun.e99.a.2500","DOI":"10.1587\/transfun.E99.A.2500"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] Q. Zhao, K. Yanagida, M. Amagasaki, M. Iida, M. Kuga, and T. Sueyoshi, \u201cA logic cell architecture exploiting the Shannon expansion for the reduction of configuration memory,\u201d 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-6, IEEE, 2014. 10.1109\/fpl.2014.6927460","DOI":"10.1109\/FPL.2014.6927460"},{"key":"3","unstructured":"[3] S.Takagi, N.Niwa, Y.Yanai, H.Amano, M.Amagasaki, Y.Nakazato, and M.Iida, \u201cTag-less compression for FPGA configuration data,\u201d Proc. of SASIMI 2022, pp.1-2, 2022."},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] S. Hauck and W.D. Wilson, \u201cRunlength compression techniques for FPGA configurations,\u201d Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. no.PR00375), pp.286-287, IEEE, 1999. 10.1109\/fpga.1999.803700","DOI":"10.1109\/FPGA.1999.803700"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] A. Dandalis and V.K. Prasanna, \u201cConfiguration compression for FPGA-based embedded systems,\u201d Proceedings of the 2001 ACM\/SIGDA ninth international symposium on Field programmable gate arrays, pp.173-182, 2001. 10.1145\/360276.360342","DOI":"10.1145\/360276.360342"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] R. Jia, F. Wang, R. Chen, X.-G. Wang, and H.-G. Yang, \u201cJTAG-based bitstream compression for FPGA configuration,\u201d 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, pp.1-3, IEEE, 2012. 10.1109\/icsict.2012.6467807","DOI":"10.1109\/ICSICT.2012.6467807"},{"key":"7","unstructured":"[7] A. Alameldeen and D. Wood, \u201cFrequent pattern compression: A significance-based compression scheme for l2 caches,\u201d tech. rep., University of Wisconsin-Madison Department of Computer Sciences, 2004."},{"key":"8","unstructured":"[8] A. Khu, \u201cXilinx FPGA Configuration Data Compression and Decompression,\u201d tech. rep., Sept. 2001."},{"key":"9","unstructured":"[9] E. Thacker, \u201cSystem Ace: Configuration Solution for Xilinx FPGAs,\u201d tech. rep., Sept. 2001."},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] S. Hauck, Z. Li, and E. Schwabe, \u201cConfiguration compression for the Xilinx XC6200 FPGA,\u201d Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. no.98TB100251), pp.138-146, IEEE, 1998. 10.1109\/fpga.1998.707891","DOI":"10.1109\/FPGA.1998.707891"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] X. Jing, W. Yabin, C. Liguang, W. Jian, W. Yuan, L. Jinmei, and T. Jiarong, \u201cFast configuration architecture of FPGA suitable for bitstream compression,\u201d 2009 IEEE 8th International Conference on ASIC, pp.126-130, IEEE, 2009.","DOI":"10.1109\/ASICON.2009.5351590"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] K. Tanigawa, T. Kawasaki, and T. Hironaka, \u201cA coarse-grained reconfigurable architecture with low cost configuration data compression mechanism,\u201d Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT)(IEEE Cat. no.03EX798), pp.311-314, IEEE, 2003. 10.1109\/fpt.2003.1275765","DOI":"10.1109\/FPT.2003.1275765"},{"key":"13","doi-asserted-by":"publisher","unstructured":"[13] M. Kuga, Q. Zhao, Y. Nakazato, M. Amagasaki, and M. Iida, \u201cAn eFPGA Generation Suite with Customizable Architecture and IDE,\u201d IEICE Trans. Fundamentals, vol.E106-A, no.3, pp.560-574, 2023. 10.1587\/transfun.2022vlp0008","DOI":"10.1587\/transfun.2022VLP0008"},{"key":"14","unstructured":"[14] S. Yang, \u201cLogic synthesis and optimization benchmarks user guide: Version 3.0,\u201d tech. rep., MCNC Technical Report, Jan. 1991."},{"key":"15","unstructured":"[15] C. Albrecht, \u201cIWLS 2005 Benchmarks,\u201d tech. rep., June 2005."},{"key":"16","doi-asserted-by":"publisher","unstructured":"[16] Q. Zhao, M. Amagasaki, M. Iida, M. Kuga, and T. Sueyoshi, \u201cTowards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost,\u201d IPSJ Transactions on System LSI Design Methodology, vol.10, pp.63-70, 2017. 10.2197\/ipsjtsldm.10.63","DOI":"10.2197\/ipsjtsldm.10.63"},{"key":"17","unstructured":"[17] A. Alameldeen and D. Wood, \u201cFrequent pattern compression: A significance-based compression scheme for l2 caches,\u201d tech. rep., University of Wisconsin-Madison Department of Computer Sciences, 2004."}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E107.D\/12\/E107.D_2024EDP7033\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,7]],"date-time":"2024-12-07T03:24:59Z","timestamp":1733541899000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E107.D\/12\/E107.D_2024EDP7033\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,1]]},"references-count":17,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2024]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2024edp7033","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,12,1]]},"article-number":"2024EDP7033"}}