{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,5,29]],"date-time":"2023-05-29T09:11:18Z","timestamp":1685351478230},"reference-count":1,"publisher":"National Library of Serbia","issue":"1","license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["ComSIS","COMPUT SCI INF SYST","COMPUT SCI INFORM SY","COMPUTER SCI INFORM","COMSIS J"],"published-print":{"date-parts":[[2010]]},"abstract":"<jats:p>As a video coding standard, H.264 achieves high compress rate while keeping good fidelity. But it requires more intensive computation than before to get such high coding performance. A Hierarchical Multi-level Parallelisms (HMLP) framework for H.264 encoder is proposed which integrates four level parallelisms - frame-level, slice-level, macroblock-level and data-level into one implementation. Each level parallelism is designed in a hierarchical parallel framework and mapped onto the multi-cores and SIMD units on multi-core architecture. According to the analysis of coding performance on each level parallelism, we propose a method to combine different parallel levels to attain a good compromise between high speedup and low bit-rate. The experimental results show that for CIF format video, our method achieves the speedup of 33.57x-42.3x with 1.04x-1.08x bit-rate increasing on 8-core Intel Xeon processor with SIMD Technology.<\/jats:p>","DOI":"10.2298\/csis1001189w","type":"journal-article","created":{"date-parts":[[2010,4,14]],"date-time":"2010-04-14T08:51:07Z","timestamp":1271235067000},"page":"189-200","source":"Crossref","is-referenced-by-count":1,"title":["The design and evaluation of hierarchical multi-level parallelisms for H.264 encoder on multi-core architecture"],"prefix":"10.2298","volume":"7","author":[{"given":"Haitao","family":"Wei","sequence":"first","affiliation":[{"name":"School of Computer Science & Technology, Huazhong University of Science & Technology, Wuhan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Junqing","sequence":"additional","affiliation":[{"name":"School of Computer Science & Technology, Huazhong University of Science & Technology, Wuhan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li","family":"Jiang","sequence":"additional","affiliation":[{"name":"School of Computer Science & Technology, Huazhong University of Science & Technology, Wuhan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1078","reference":[{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2003.815165"}],"container-title":["Computer Science and Information Systems"],"original-title":[],"language":"en","deposited":{"date-parts":[[2023,5,29]],"date-time":"2023-05-29T08:30:03Z","timestamp":1685349003000},"score":1,"resource":{"primary":{"URL":"https:\/\/doiserbia.nb.rs\/Article.aspx?ID=1820-02141001189W"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"references-count":1,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2010]]}},"URL":"https:\/\/doi.org\/10.2298\/csis1001189w","relation":{},"ISSN":["1820-0214","2406-1018"],"issn-type":[{"value":"1820-0214","type":"print"},{"value":"2406-1018","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010]]}}}