{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:43:24Z","timestamp":1750308204651,"version":"3.41.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7926955","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T20:34:41Z","timestamp":1494880481000},"page":"37-42","source":"Crossref","is-referenced-by-count":5,"title":["Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores"],"prefix":"10.23919","author":[{"given":"Arun","family":"Subramaniyan","sequence":"first","affiliation":[]},{"given":"Semeen","family":"Rehman","sequence":"additional","affiliation":[]},{"given":"Muhammad","family":"Shafique","sequence":"additional","affiliation":[]},{"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[]},{"given":"Jorg","family":"Henkel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"796","article-title":"Finding optimal L1 cache configuration for embedded systems","author":"janapsatya","year":"2006","journal-title":"ASP-DAC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.7873\/DATE2014.296"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.44"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118507"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/993396.993405"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"221","DOI":"10.3233\/EMC-2006-00027","article-title":"A dynamically reconfigurable cache for multithreaded processors","volume":"2","author":"settle","year":"2006","journal-title":"Embedded Computing"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref17","first-page":"29","article-title":"A systematic methodology to compute the architecturalvul-nerabilityfactors for a high-performance microprocessor","author":"mukherjee","year":"2003","journal-title":"Micro"},{"key":"ref18","article-title":"R2Cache: reliability-aware reconfigurable last-level cache architecture for multi-cores","author":"kriebel","year":"2015","journal-title":"CODES+ISSS"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2961059"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.23"},{"key":"ref27","first-page":"461","article-title":"Energy-efficient cache design using variable-strength er-ror-correcting codes","author":"alameldeen","year":"2011","journal-title":"ISCA"},{"key":"ref3","first-page":"1171","article-title":"On the characterization and optimization of on-chip cache reliability against soft errors","volume":"58","author":"wang","year":"2009","journal-title":"IEEE TC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024935"},{"journal-title":"CACTI 6 5","year":"0","key":"ref29"},{"key":"ref5","first-page":"293","article-title":"Calculating ArchitecturalVulnerability Factors for Spatial Multi-Bit Transient Faults","author":"wilkening","year":"2014","journal-title":"IEEE MICRO-47"},{"key":"ref8","first-page":"208","article-title":"Automatic tuning of two-level caches to embedded applications","author":"gordon-ross","year":"2004","journal-title":"DATE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657056"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2047907"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344610"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2505012"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485949"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1993744.1993755"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2011.1113"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2013.6575314"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.244100"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2017,3,27]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07926955.pdf?arnumber=7926955","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:27:50Z","timestamp":1750264070000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7926955\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":29,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7926955","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}