{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T00:08:18Z","timestamp":1780445298034,"version":"3.54.1"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7926996","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T16:34:41Z","timestamp":1494866081000},"page":"270-273","source":"Crossref","is-referenced-by-count":8,"title":["Analog fault testing through abstraction"],"prefix":"10.23919","author":[{"given":"Enrico","family":"Fraccaroli","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Franco","family":"Fummi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"913","article-title":"Fault macromodeling for analog\/mixed-signal circuits","author":"pan","year":"0","journal-title":"Test Conference 1997 Proceedings International Int Test Conference"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1982.4336490"},{"key":"ref12","article-title":"Verilog-AMS Language Reference Manual","year":"0","journal-title":"Accellera Systems Initiative"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2010.5496665"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2173492"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2000.889554"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-58426-9_132"},{"key":"ref5","first-page":"1586","article-title":"Integration of Mixed-Signal Components into Virtual Platforms for Holistic Simulation of Smart Systems","author":"enrico fraccaroli","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref8","author":"scheffer","year":"2006","journal-title":"EDA for IC Implementation Circuit Design and Process Technology"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268909"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCIS.2010.101"},{"key":"ref1","first-page":"177","article-title":"Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation","volume":"39","author":"kili\u00e7","year":"0","journal-title":"Journal of AICSP 2004"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1994.528009"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Lausanne, Switzerland","start":{"date-parts":[[2017,3,27]]},"end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07926996.pdf?arnumber=7926996","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T21:53:59Z","timestamp":1506981239000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7926996\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":13,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7926996","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}