{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T08:29:37Z","timestamp":1775809777196,"version":"3.50.1"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7927013","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T20:34:41Z","timestamp":1494880481000},"page":"338-343","source":"Crossref","is-referenced-by-count":57,"title":["Exploiting transistor-level reconfiguration to optimize combinational circuits"],"prefix":"10.23919","author":[{"given":"Michael","family":"Raitza","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marcus","family":"Volp","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dennis","family":"Walter","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jens","family":"Trommer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas","family":"Mikolajick","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Walter M.","family":"Weber","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","author":"sutherland","year":"1999","journal-title":"Logical Effort Designing Fast CMOS Circuits"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2290555"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2015.2429893"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1557\/opl.2014.110"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0206"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDER.2006.307728"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2333675"},{"key":"ref17","first-page":"2111","article-title":"Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs","author":"zhang","year":"2013","journal-title":"ISCAS"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2359112"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024921"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2359385"},{"key":"ref3","first-page":"343","article-title":"A new direct design for three-input XOR function on the transistor level","author":"fang","year":"1996","journal-title":"TCAS i"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1021\/nl401826u"},{"key":"ref5","first-page":"235:1","article-title":"Advanced System on a Chip Design Based on Controllable-polarity FETs","author":"gaillardon","year":"2014","journal-title":"DATE"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479004"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1021\/nl203094h"},{"key":"ref2","first-page":"975","article-title":"Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications","author":"cheng","year":"2006","journal-title":"J Inform Sci Eng"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCSCE.2015.7482151"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.spmi.2016.01.032"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Lausanne, Switzerland","start":{"date-parts":[[2017,3,27]]},"end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07927013.pdf?arnumber=7927013","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,3]],"date-time":"2017-10-03T01:49:24Z","timestamp":1506995364000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927013\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":19,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7927013","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}