{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:42:48Z","timestamp":1729622568100,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7927026","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T20:34:41Z","timestamp":1494880481000},"page":"416-421","source":"Crossref","is-referenced-by-count":0,"title":["An open reconfigurable research platform as stepping stone to exascale high-performance computing"],"prefix":"10.23919","author":[{"given":"Dirk","family":"Stroobandt","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Catalin Bogdan","family":"Ciobanu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco D.","family":"Santambrogio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gabriel","family":"Figueiredo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Brokalakis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dionisios","family":"Pnevmatikatos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Huebner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tobias","family":"Becker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex J. W.","family":"Thom","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Xilinx Redefines Power Performance and Design Productivity with Three New 28 nm FPGA Families Virtex-7 Kintex-7 and Artix-7 Devices Xilinx White Paper WP373 (v1 0)","year":"2010","author":"przybus","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.cpc.2007.03.004"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2010.122"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.cpc.2014.09.016"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"321","DOI":"10.1016\/j.micpro.2014.09.006","article-title":"Faster: facilitating analysis and synthesis technologies for effective reconfiguration","volume":"39","author":"pnevmatikatos","year":"2014","journal-title":"Microprocessors and Microsystems"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927497"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689076"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.36"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1190\/segam2012-1282.1"},{"journal-title":"IBM Forging Bigger Power8 Systems Adding FPGA Acceleration","year":"2014","author":"morgan","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4629896"},{"journal-title":"How Intel is Hedging on the Future of Compute with Altera Buy","year":"2014","author":"morgan","key":"ref8"},{"journal-title":"Microsoft ‘Catapults’ geriatric Moore's Law from CERTAIN DEATH FPGAs DOUBLE data center throughput despite puny power pump-up we're told","year":"2014","author":"clark","key":"ref7"},{"key":"ref2","first-page":"97","article-title":"Automating elimination of idle functions by run-time reconfiguration","author":"niu","year":"2013","journal-title":"FCCM 2013"},{"key":"ref1","article-title":"Project Genome: Wireless Sensor Network for Data Center Cooling","author":"liu","year":"2008","journal-title":"The Architecture Journal"},{"journal-title":"Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs Altera White Paper WP-01137-1 0","year":"2010","key":"ref9"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2017,3,27]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07927026.pdf?arnumber=7927026","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,24]],"date-time":"2019-09-24T17:38:32Z","timestamp":1569346712000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927026\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":17,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7927026","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}