{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:41:57Z","timestamp":1773247317496,"version":"3.50.1"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7927038","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T16:34:41Z","timestamp":1494866081000},"page":"488-493","source":"Crossref","is-referenced-by-count":38,"title":["DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling"],"prefix":"10.23919","author":[{"given":"Bert","family":"Moons","sequence":"first","affiliation":[]},{"given":"Roel","family":"Uytterhoeven","sequence":"additional","affiliation":[]},{"given":"Wim","family":"Dehaene","sequence":"additional","affiliation":[]},{"given":"Marian","family":"Verhelst","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1038\/nature14539"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870353"},{"key":"ref12","first-page":"178","article-title":"A 0.3&#x2013;2.6 tops\/w precision-scalable processor for real-time large-scale convnets","author":"moons","year":"2016","journal-title":"Proceedings of the IEEE Symposium on VLSI Circuits"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224083"},{"key":"ref14","article-title":"Rapidarchitectural exploration in designing application-specific processors","author":"wu","year":"2015","journal-title":"ASIP Designer whitepaper"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750389"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2743766"},{"key":"ref18","doi-asserted-by":"crossref","DOI":"10.1145\/3007787.3001163","article-title":"EIE: efficient inference engine on compressed deep neural network","author":"han","year":"2016","journal-title":"International Symposium on Computer Architecture (ISCA)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657019"},{"key":"ref28","author":"sun","year":"2016","journal-title":"Intra-layernonuniform quantization for deep convolutional neural network"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.51"},{"key":"ref27","first-page":"1097","article-title":"Imagenet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proceedings of Advances in Neural Information Processing Systems"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2014.108"},{"key":"ref6","article-title":"A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision","author":"camus","year":"2016","journal-title":"Design Automation Conference (DAC) 2016 53rd ACM\/EDAC\/IEEE"},{"key":"ref29","volume":"abs 1409 1556","author":"simonyan","year":"2014","journal-title":"Very Deep Convolutional Networks for Large-scale Image Recognition"},{"key":"ref5","article-title":"Low-power high-speed multiplier for error-tolerant application","author":"kyaw","year":"2011","journal-title":"Electron Devices and Solid-State Circuits"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2189059"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2015.7273520"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488873"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2013.6569370"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540710"},{"key":"ref20","volume":"abs 1602 7360","author":"iandola","year":"2016","journal-title":"SqueezeNet AlexNet-level accuracy with 50x fewer parameters and"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/WACV.2016.7477614"},{"key":"ref21","first-page":"1135","article-title":"Learning both weights and connections for efficient neural network","author":"han","year":"2015","journal-title":"Proceedings of Advances in Neural Information Processing Systems"},{"key":"ref24","volume":"abs 1602 2830","author":"courbariaux","year":"2016","journal-title":"BinaryNet Training Deep Neural Networks with Weights and Activations Constrained to +1 or ?1"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573527"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref25","article-title":"Hardware-oriented approximation of convolutional neural networks","author":"gysel","year":"2016","journal-title":"Workshop contribution to International Conference on Learning Representations (ICLR)"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Lausanne, Switzerland","start":{"date-parts":[[2017,3,27]]},"end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07927038.pdf?arnumber=7927038","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,24]],"date-time":"2019-09-24T13:38:47Z","timestamp":1569332327000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927038\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":29,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7927038","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}