{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:25:49Z","timestamp":1763724349157,"version":"3.28.0"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7927041","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T16:34:41Z","timestamp":1494866081000},"page":"506-511","source":"Crossref","is-referenced-by-count":8,"title":["Performance impacts and limitations of hardware memory access trace collection"],"prefix":"10.23919","author":[{"given":"Nicholas C.","family":"Doyle","sequence":"first","affiliation":[]},{"given":"Eric","family":"Matthews","sequence":"additional","affiliation":[]},{"given":"Graham","family":"Holland","sequence":"additional","affiliation":[]},{"given":"Alexandra","family":"Fedorova","sequence":"additional","affiliation":[]},{"given":"Lesley","family":"Shannon","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","first-page":"53","article-title":"Memprof: A memory profiler for numa multicore systems","author":"lachaize","year":"0","journal-title":"Proc USENIX Annual Technical Conf 2012"},{"journal-title":"MicroBlaze Processor Reference Guide","year":"0","key":"ref32"},{"journal-title":"Tech Rep UG585","article-title":"Zynq-7000 all programmable soc technical reference manual","year":"2015","key":"ref31"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"156","DOI":"10.1145\/2684746.2689083","article-title":"Design space exploration of 11 data caches for fpga-based multiprocessor systems","author":"matthews","year":"2015","journal-title":"Proc 2015 ACM\/SIGDA Int Symp Field-Programmable Gate Arrays"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451157"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488831"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2011.6043237"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1952522.1952525"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927437"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2014.2321398"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636099"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919635"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557172"},{"journal-title":"Intel vtune amplifier 2016","year":"2016","author":"corporation","key":"ref18"},{"journal-title":"Codexl Powerful debugging profiling and analysis","year":"2016","key":"ref19"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681447"},{"volume":"2","journal-title":"AMD64 Architecture Programmer's Manual","year":"2015","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1945023.1945034"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"64:1","DOI":"10.1145\/2435227.2435260","article-title":"Timing effects of ddr memory systems in hard real-time multicore architectures: Issues and solutions","volume":"12","author":"paolieri","year":"2013","journal-title":"ACM Trans Embed Comput Syst"},{"journal-title":"ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition","year":"2014","key":"ref6"},{"key":"ref29","volume":"abs 1508 7126","author":"shannon","year":"2015","journal-title":"Performance monitoring for multicore embedded computing systems on fpgas"},{"volume":"3b","journal-title":"Intel IA-64 Architecture Software Developer s Manual","year":"2015","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451128"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000084"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339185"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2046582.2046596"},{"journal-title":"Benchmarking Modern Multiprocessors","year":"2011","author":"bienia","key":"ref1"},{"key":"ref20","article-title":"Performance tools developments","author":"vitillo","year":"2011","journal-title":"Future computing in particle physics"},{"journal-title":"Tech Rep 43724","article-title":"Lightweight profiling specification","year":"2010","key":"ref22"},{"volume":"3c","journal-title":"Intel IA-64 Architecture Software Developer s Manual","year":"2015","key":"ref21"},{"journal-title":"Tech Rep ARM-EPM-039795","article-title":"Coresight technical introduction","year":"2013","key":"ref24"},{"journal-title":"Tech Rep ARM-IHI-0064D","article-title":"Arm embedded trace macrocell architecture specification","year":"2016","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750401"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1181309.1181319"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2017,3,27]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07927041.pdf?arnumber=7927041","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,24]],"date-time":"2019-09-24T13:38:47Z","timestamp":1569332327000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927041\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":34,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7927041","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}