{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:46:41Z","timestamp":1729644401191,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7927062","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T20:34:41Z","timestamp":1494880481000},"page":"622-625","source":"Crossref","is-referenced-by-count":4,"title":["SPMS: Strand based persistent memory system"],"prefix":"10.23919","author":[{"given":"Shuo","family":"Li","sequence":"first","affiliation":[]},{"given":"Peng","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Nong","family":"Xiao","sequence":"additional","affiliation":[]},{"given":"Guangyu","family":"Sun","sequence":"additional","affiliation":[]},{"given":"Fang","family":"Liu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446055"},{"journal-title":"Micron Technology Inc NVDIMM DRAM Modules","year":"0","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974684"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"ACM SIGARCH Comput Arch News"},{"journal-title":"Boost Graph Library Adjacency List - 1 59 0","year":"0","author":"siek","key":"ref14"},{"key":"ref15","first-page":"465","article-title":"Design and Implementation of the HPCS Graph Analysis Benchmark on Symmetric Multiprocessors","author":"bader","year":"2005","journal-title":"HiPC"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950379"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950380"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853222"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629589"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783761"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540744"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830802"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522726"},{"journal-title":"Intel Architecture Instruction Set Extensions Programming Reference","year":"2016","key":"ref9"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2017,3,27]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07927062.pdf?arnumber=7927062","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,24]],"date-time":"2019-09-24T17:37:42Z","timestamp":1569346662000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927062\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7927062","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}