{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T09:43:22Z","timestamp":1772358202953,"version":"3.50.1"},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7927084","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T16:34:41Z","timestamp":1494866081000},"page":"732-733","source":"Crossref","is-referenced-by-count":13,"title":["An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart"],"prefix":"10.23919","author":[{"given":"Weiwei","family":"Jiang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Bertozzi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gabriele","family":"Miorandi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven M.","family":"Nowick","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Burleson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Greg","family":"Sadowski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"668","DOI":"10.1126\/science.1254642","article-title":"A million spiking-neuron integrated circuit with a scalable communication network and interface","volume":"345","author":"merolla","year":"2014","journal-title":"Science"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228568"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2413759"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2014.7004164"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2015.7250461"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.079"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Lausanne, Switzerland","start":{"date-parts":[[2017,3,27]]},"end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07927084.pdf?arnumber=7927084","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,24]],"date-time":"2019-09-24T13:37:54Z","timestamp":1569332274000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927084\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":6,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7927084","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}