{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T07:42:38Z","timestamp":1761896558266,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7927151","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T16:34:41Z","timestamp":1494866081000},"page":"1086-1091","source":"Crossref","is-referenced-by-count":11,"title":["MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems"],"prefix":"10.23919","author":[{"given":"Di","family":"Chen","sequence":"first","affiliation":[]},{"given":"Hai","family":"Jin","sequence":"additional","affiliation":[]},{"given":"Xiaofei","family":"Liao","sequence":"additional","affiliation":[]},{"given":"Haikun","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Rentong","family":"Guo","sequence":"additional","affiliation":[]},{"given":"Dong","family":"Liu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TSMC.1979.4310076"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The GEM5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835921"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540733"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835944"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000073"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830802"},{"key":"ref3","first-page":"234","article-title":"i2 wap: Improving nonvolatile cache lifetime by reducing inter- and intra-set write variations","author":"wang","year":"2013","journal-title":"Proc of HPCA"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540744"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669164"},{"key":"ref7","first-page":"452","article-title":"Zombie memory: extending memory lifetime by reviving dead blocks","author":"azevedo","year":"2013","journal-title":"Proc of ISCA"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485929"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974658"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2555307"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2017,3,27]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07927151.pdf?arnumber=7927151","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,24]],"date-time":"2019-09-24T13:38:37Z","timestamp":1569332317000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927151\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7927151","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}