{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T02:44:41Z","timestamp":1730342681509,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7927189","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T16:34:41Z","timestamp":1494866081000},"page":"1281-1284","source":"Crossref","is-referenced-by-count":3,"title":["Automatic technology migration of analog IC designs using generic cell libraries"],"prefix":"10.23919","author":[{"given":"Jose","family":"Cachaco","sequence":"first","affiliation":[]},{"given":"Nuno","family":"Machado","sequence":"additional","affiliation":[]},{"given":"Nuno","family":"Lourenco","sequence":"additional","affiliation":[]},{"given":"Jorge","family":"Guilherme","sequence":"additional","affiliation":[]},{"given":"Nuno","family":"Horta","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2012.6330571"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654159"},{"key":"ref10","first-page":"194","article-title":"Low-power transistor-string and new rail-to-rail comparator in a\/d converter","volume":"1","author":"park","year":"0","journal-title":"Circuits and Systems 1999 42nd Midwest Symposium on"},{"key":"ref6","article-title":"(2015) Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction","author":"lourenco","year":"2015","journal-title":"Design Automation & Test in Europe Conference & Exhibition (DATE) 2015"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.04.009"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.7873\/DATE2014.027"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2158732"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717781"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008349731160"},{"key":"ref1","article-title":"Analog circuits and systems optimization based on evolutionary computation techniques","author":"barros","year":"2010","journal-title":"Springer"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2017,3,27]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07927189.pdf?arnumber=7927189","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T14:56:47Z","timestamp":1513177007000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927189\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":10,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7927189","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}