{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,17]],"date-time":"2025-09-17T14:46:43Z","timestamp":1758120403392},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.23919\/date.2017.7927275","type":"proceedings-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T20:34:41Z","timestamp":1494880481000},"page":"1745-1750","source":"Crossref","is-referenced-by-count":2,"title":["Fast low power rule checking for multiple power domain design"],"prefix":"10.23919","author":[{"given":"Chien-Pang","family":"Lu","sequence":"first","affiliation":[]},{"given":"Iris Hui-Ru","family":"Jiang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"53","article-title":"Power assertions and coverage for improving quality of low power verification and closure of power intent","author":"khan","year":"2008","journal-title":"Proc DVCON"},{"key":"ref11","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871603"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243858"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2009.85"},{"journal-title":"Advanced Configuration and Power Interface (ACPI)","year":"0","key":"ref15"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837469"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2180548"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2009.5404109"},{"key":"ref5","first-page":"42","article-title":"Static and formal verification of power aware designs at the RTL using UPF","author":"mukherjee","year":"2008","journal-title":"Proc DVCON"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2009.5397836"},{"key":"ref7","first-page":"1","article-title":"Mixed-signal verification methods for multi-power mixed-signal System-on-Chip (SoC) design","author":"liang","year":"2013","journal-title":"Proc ASICON"},{"key":"ref2","first-page":"228","article-title":"Low power verification methodology using UPF","author":"bembaron","year":"2009","journal-title":"Proc DVCON"},{"journal-title":"IEEE Standard for Design and Verification of Low-Power Integrated Circuits","year":"0","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397241"}],"event":{"name":"2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2017,3,27]]},"location":"Lausanne, Switzerland","end":{"date-parts":[[2017,3,31]]}},"container-title":["Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7919927\/7926947\/07927275.pdf?arnumber=7927275","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,5,31]],"date-time":"2017-05-31T04:22:08Z","timestamp":1496204528000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7927275\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.23919\/date.2017.7927275","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}