{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T19:31:29Z","timestamp":1725737489809},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8341989","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T23:20:11Z","timestamp":1524525611000},"page":"113-118","source":"Crossref","is-referenced-by-count":4,"title":["Spintronic normally-off heterogeneous system-on-chip design"],"prefix":"10.23919","author":[{"given":"Anteneh","family":"Gebregiorgis","sequence":"first","affiliation":[]},{"given":"Rajendra","family":"Bishnoi","sequence":"additional","affiliation":[]},{"given":"Mehdi B.","family":"Tahoori","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744842"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3001936"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2295026"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2013","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2391254"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2015.2509963"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757392"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428104"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1038\/nmat3051"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1063\/1.4863407"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2496363"},{"key":"ref4","article-title":"A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-urn CMOS for Nonvolatile processing in Digital Systems","author":"qazi","year":"2014","journal-title":"JSSC"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.07.001"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2012.6341281"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2700788"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCDG.2013.6656320"},{"key":"ref5","article-title":"An 8mhz 75 ua\/mhz zero-leakage non-volatile logicbased cortex-m0 mcu soc exhibiting 100lt; 400ns wakeup and sleep transitions","author":"bartling","year":"2013","journal-title":"ISSCC"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2013.6691046"},{"key":"ref7","article-title":"4.7 A 65nm ReRAM-enabled nonvolatile processor with 6X reduction in restore time and 4X higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic","author":"liu","year":"2016","journal-title":"ISSCC"},{"journal-title":"As nodes advance so must power analysis","year":"2014","author":"singh","key":"ref2"},{"key":"ref9","article-title":"A compression-based area-efficient recovery architecture for nonvolatile processors","author":"wang","year":"2012","journal-title":"DATE"},{"journal-title":"Low-Voltage Low-Power VLSI Subsystems","year":"2005","author":"yeo","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1063\/1.4902443"},{"journal-title":"Freescale Wireless Low-Power Design and Verification With CPF","year":"0","author":"padhye","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DSNW.2011.5958839"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2016.2541629"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1186\/1556-276X-9-526"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2903022"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2630315"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08341989.pdf?arnumber=8341989","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T15:14:15Z","timestamp":1525446855000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8341989\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":29,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8341989","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}