{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,15]],"date-time":"2025-12-15T14:05:48Z","timestamp":1765807548074,"version":"3.28.0"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342027","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T23:20:11Z","timestamp":1524525611000},"page":"309-314","source":"Crossref","is-referenced-by-count":25,"title":["Practical exact synthesis"],"prefix":"10.23919","author":[{"given":"Mathias","family":"Soeken","sequence":"first","affiliation":[]},{"given":"Winston","family":"Haaswijk","sequence":"additional","affiliation":[]},{"given":"Eleonora","family":"Testa","sequence":"additional","affiliation":[]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[]},{"given":"Luca G.","family":"Amaru","sequence":"additional","affiliation":[]},{"given":"Robert K.","family":"Brayton","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675229"},{"key":"ref10","first-page":"154","article-title":"Counterexample-guided abstraction refinement","author":"clarke","year":"2000","journal-title":"Computer Aided Verification"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1996.563527"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2664059"},{"key":"ref13","article-title":"Exact synthesis for logic synthesis applications with complex constraints","author":"testa","year":"2017","journal-title":"Int'l Workshop on Logic and Synthesis"},{"key":"ref14","first-page":"1092","article-title":"Experimental results on the application of satisfiability algorithms to scheduling problems","author":"crawford","year":"1994","journal-title":"National Conf on Artificial Intelligence"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203799"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927103"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429513"},{"journal-title":"Optimal combinational multi-level logic synthesis","year":"2009","author":"ernst","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.1961.1"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674714"},{"journal-title":"Handbook of Satisfiability","year":"2009","author":"biere","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5008920"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1949.tb03624.x"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-02777-2_5"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1969.222593"},{"journal-title":"The Art of Computer Programming Volume 4 Fascicle 6 Satisfiability","year":"2015","author":"knuth","key":"ref5"},{"key":"ref8","first-page":"151","article-title":"A novel basis for logic optimization","author":"haaswijk","year":"2017","journal-title":"Asia and South Pacific Design Automation Conference"},{"key":"ref7","article-title":"Practical SAT - a tutorial on applied satisfiability solving","author":"\u00e9en","year":"0","journal-title":"2007 slides of invited talk at FMCAD"},{"key":"ref2","volume":"4a","author":"knuth","year":"2011","journal-title":"The art of computer programming"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2017.44"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5139-3"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1147\/rd.62.0227"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/321229.321232"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1968.227399"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1965.264064"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1963.263531"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5009010"},{"key":"ref25","article-title":"Exact circuit synthesis","author":"drechsler","year":"1998","journal-title":"Int'l Workshop on Logic and Synthesis"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342027.pdf?arnumber=8342027","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T15:12:16Z","timestamp":1525446736000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342027\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":31,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342027","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}