{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,21]],"date-time":"2026-05-21T11:48:59Z","timestamp":1779364139707,"version":"3.53.0"},"reference-count":33,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342045","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T19:20:11Z","timestamp":1524511211000},"page":"413-418","source":"Crossref","is-referenced-by-count":33,"title":["PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture"],"prefix":"10.23919","author":[{"given":"Omid","family":"Akbari","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mehdi","family":"Kamal","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ali","family":"Afzali-Kusha","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Massoud","family":"Pedram","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Muhammad","family":"Shafique","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","author":"de micheli","year":"1994","journal-title":"Synthesis and Optimization of Digital Circuits"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744863"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488756"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927209"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2643003"},{"key":"ref11","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","author":"esmaeilzadeh","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593094"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488949"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.75"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"ref16","year":"0","journal-title":"The “Standard Cell Library Optimization Company"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2505723"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2893356"},{"key":"ref19","first-page":"124","article-title":"Low-Power Digital Signal Proccessing Using Approximate Adders","volume":"32","author":"gupta","year":"2013","journal-title":"IEEE TCAD"},{"key":"ref28","first-page":"217","article-title":"Low-Power Reconfigurable Processor Utilizing Variable Dual VDD","volume":"60","author":"zhu","year":"2013","journal-title":"IEEE TCAS II"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2044667"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523597"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2008.4570782"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456939"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19475-7_24"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062262"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2906199"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/518659"},{"key":"ref2","first-page":"1475","article-title":"Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual-Vdd CGRAs","volume":"35","author":"yin","year":"2016","journal-title":"IEEE TCAD"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2633307"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TMM.2015.2463735"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691096"},{"key":"ref22","first-page":"1449","article-title":"A new approximate adder with low relative error and correct sign calculation","author":"hu","year":"2015","journal-title":"IEEE DATE"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744778"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2308214"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.51"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2016.7818353"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1155\/2013\/683615"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Dresden","start":{"date-parts":[[2018,3,19]]},"end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342045.pdf?arnumber=8342045","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,28]],"date-time":"2018-05-28T20:03:00Z","timestamp":1527537780000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8342045\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":33,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342045","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}