{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,30]],"date-time":"2026-03-30T17:03:03Z","timestamp":1774890183739,"version":"3.50.1"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342047","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T19:20:11Z","timestamp":1524511211000},"page":"425-430","source":"Crossref","is-referenced-by-count":5,"title":["Logic synthesis and defect tolerance for memristive crossbar arrays"],"prefix":"10.23919","author":[{"given":"Onur","family":"Tunali","sequence":"first","affiliation":[]},{"given":"Mustafa","family":"Altun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2017.7934559"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818762"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.206"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2602804"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3125641"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1038\/nmat3070"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2038539"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2017.7934557"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2016.7753567"},{"key":"ref19","article-title":"Verification group","author":"ssynthesis","year":"2013","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3149-1"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2016.2583673"},{"key":"ref8","article-title":"A mapping methodology of boolean logic circuits on memristor crossbar","volume":"99","author":"xie","year":"2017","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357122"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2012.240"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1021\/nl203687n"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/PRIME.2016.7519463"},{"key":"ref20","article-title":"Iwls&#x00E2;??93 benchmark set: Version 4.0","volume":"93","author":"mcelvain","year":"1993","journal-title":"Distributed as part of the MCNC International Workshop on Logic Synthesis"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1137\/0105003"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Dresden, Germany","start":{"date-parts":[[2018,3,19]]},"end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342047.pdf?arnumber=8342047","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T11:09:27Z","timestamp":1525432167000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342047\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":21,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342047","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}