{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,3]],"date-time":"2025-12-03T17:47:50Z","timestamp":1764784070859,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342053","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T19:20:11Z","timestamp":1524511211000},"page":"461-466","source":"Crossref","is-referenced-by-count":11,"title":["LARS: Logically adaptable retention time STT-RAM cache for embedded systems"],"prefix":"10.23919","author":[{"given":"Kyle","family":"Kuan","sequence":"first","affiliation":[]},{"given":"Tosiron","family":"Adegbija","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753282"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2224256"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","article-title":"Spec cpu2006 benchmark descriptions","volume":"34","author":"henning","year":"2006","journal-title":"SIGARCH Comput Archit News"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2742076"},{"journal-title":"Cortex-A15 Processor","year":"0","key":"ref14"},{"key":"ref15","first-page":"234","article-title":"A self-tuning configurable cache","author":"gordon-ross","year":"2007","journal-title":"Proceedings of the 44th Annual Design Automation Conference"},{"journal-title":"Synopsys Inc","year":"2000","author":"compiler","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2693433.2693440"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155659"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"554","DOI":"10.1145\/1391469.1391610","article-title":"circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement","author":"xiangyu dong","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105369"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/19\/16\/165209"},{"key":"ref8","first-page":"273","article-title":"Compiler-assisted refresh minimization for volatile stt-ram cache","author":"li","year":"2013","journal-title":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749716"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.suscom.2013.11.001"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2669556"},{"journal-title":"HP Labs CACTI","year":"0","key":"ref20"},{"journal-title":"Software Development for Embedded Multi-core Systems A-Practical Guide Using Embedded Intel Architecture","year":"2011","author":"domeika","key":"ref21"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342053.pdf?arnumber=8342053","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,28]],"date-time":"2018-05-28T20:03:01Z","timestamp":1527537781000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8342053\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":21,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342053","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}