{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T05:20:50Z","timestamp":1725427250506},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342064","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T19:20:11Z","timestamp":1524511211000},"page":"527-532","source":"Crossref","is-referenced-by-count":1,"title":["MAUI: Making aging useful, intentionally"],"prefix":"10.23919","author":[{"given":"Kai-Chiang","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tien-Hung","family":"Tseng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shou-Chun","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2442087.2442098"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2195002"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2014.2315882"},{"key":"ref13","first-page":"370","article-title":"NBTI-aware synthesis of digital circuits","author":"kumar","year":"2007","journal-title":"Proc of DAC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.244119"},{"key":"ref15","first-page":"216","article-title":"Efficient transistor-level sizing technique under temporal performance degradation due to NBTI","author":"kang","year":"2007","journal-title":"Proc of ICCD"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.48"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397353"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/12.55696"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024759"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2005.08.001"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1063\/1.1567461"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.1999.799346"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2004.1315337"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008810"},{"key":"ref7","first-page":"493","article-title":"An analytical model for negative bias temperature instability","author":"kumar","year":"2006","journal-title":"Proc of ICCAD"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146959"},{"journal-title":"International Technology Roadmap for Semiconductor","year":"2013","key":"ref1"},{"key":"ref9","first-page":"327","article-title":"A novel flow for reducing clock skew considering NBTI effect and process variations","author":"chen","year":"2013","journal-title":"Proc of ISQED"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342064.pdf?arnumber=8342064","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T14:17:54Z","timestamp":1525789074000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342064\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":19,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342064","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}