{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,31]],"date-time":"2025-05-31T05:07:31Z","timestamp":1748668051913},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342069","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T19:20:11Z","timestamp":1524511211000},"page":"557-562","source":"Crossref","is-referenced-by-count":11,"title":["Task scheduling for many-cores with S-NUCA caches"],"prefix":"10.23919","author":[{"given":"Anuj","family":"Pathania","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jorg","family":"Henkel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742914"},{"key":"ref13","article-title":"Corey: An Operating System for Many Cores","author":"boyd-wickizer","year":"2008","journal-title":"Operating Systems Design and Implementation (OSDI)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1287\/opre.14.4.699"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s00373-007-0713-4"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0053978"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"ref18","article-title":"The Ondemand Governor","author":"pallipadi","year":"2006","journal-title":"the Linux Symposium"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2007.26"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1999946.1999983"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2015.29"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488734"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1248377.1248396"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.comgeo.2010.09.004"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s00453-007-9037-2"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.2200\/S00365ED1V01Y201105CAC017"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6164944"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3050437"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"319","DOI":"10.1145\/1854273.1854314","article-title":"Handling the problems and opportunities posed by multiple on-chip memory controllers","author":"awasthi","year":"2010","journal-title":"Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342069.pdf?arnumber=8342069","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,28]],"date-time":"2018-05-28T20:03:05Z","timestamp":1527537785000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8342069\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342069","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}