{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T09:54:31Z","timestamp":1764842071767},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342085","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T19:20:11Z","timestamp":1524511211000},"page":"625-628","source":"Crossref","is-referenced-by-count":17,"title":["AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory"],"prefix":"10.23919","author":[{"given":"Mimi","family":"Xie","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuangchen","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alvin Oliver","family":"Glova","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jingtong","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuangang","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"169","article-title":"53Gbps native GF(24)2 composite-field AES-encrypt\/decrypt accelerator for content-protection in 45nm highperformance microprocessors","author":"mathew","year":"2010","journal-title":"VLSIC"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/ISSCC.2010.5433948"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/HPCA.2006.1598122"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/TIFS.2016.2576903"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/JPROC.2012.2190369"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1145\/2694344.2694387"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1145\/1555754.1555759"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1145\/2000064.2000086"},{"key":"ref3","first-page":"33","article-title":"CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory","author":"chen","year":"2012","journal-title":"DATE"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1007\/978-1-4419-9551-3_2"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1145\/2694344.2694380"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1145\/2897937.2898064"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/DSD.2006.40"},{"year":"2015","journal-title":"Intel First 3D XPoint SSDs will feature up to 6GB\/s of bandwidth","key":"ref2"},{"year":"0","journal-title":"JEDEC DDR5 & NVDIMM-P Standards Under Development","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/ASPDAC.2016.7428025"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342085.pdf?arnumber=8342085","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,28]],"date-time":"2018-05-28T20:02:58Z","timestamp":1527537778000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8342085\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342085","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}