{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T10:18:05Z","timestamp":1725704285603},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342137","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T19:20:11Z","timestamp":1524511211000},"page":"905-908","source":"Crossref","is-referenced-by-count":1,"title":["Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution"],"prefix":"10.23919","author":[{"given":"Thierry","family":"Bonnoit","sequence":"first","affiliation":[]},{"given":"Fraidy","family":"Bouesse","sequence":"additional","affiliation":[]},{"given":"Nacer-Eddine","family":"Zergainoh","sequence":"additional","affiliation":[]},{"given":"Michael","family":"Nicolaidis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2014.6873672"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2007.51"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2000.876036"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.31"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2011.5783084"},{"journal-title":"LEON-3","year":"0","key":"ref15"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.838021"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2012.06.149"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2014.2388358"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803941"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2014.7027056"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2250581"},{"key":"ref9","first-page":"93","article-title":"Improved circuitry for soft error correction in combinational logic in pipelined designs","author":"krsti?","year":"2014","journal-title":"Proc IEEE IOLTS"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342137.pdf?arnumber=8342137","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T14:29:50Z","timestamp":1525789790000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342137\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342137","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}