{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T02:46:20Z","timestamp":1730342780272,"version":"3.28.0"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342143","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T23:20:11Z","timestamp":1524525611000},"page":"931-936","source":"Crossref","is-referenced-by-count":3,"title":["Using multifunctional standardized stack as universal spintronic technology for IoT"],"prefix":"10.23919","author":[{"given":"M.","family":"Tahoori","sequence":"first","affiliation":[]},{"given":"S. M.","family":"Nair","sequence":"additional","affiliation":[]},{"given":"R.","family":"Bishnoi","sequence":"additional","affiliation":[]},{"given":"S.","family":"Senni","sequence":"additional","affiliation":[]},{"given":"J.","family":"Mohdad","sequence":"additional","affiliation":[]},{"given":"F.","family":"Mailly","sequence":"additional","affiliation":[]},{"given":"L.","family":"Torres","sequence":"additional","affiliation":[]},{"given":"P.","family":"Benoit","sequence":"additional","affiliation":[]},{"given":"A.","family":"Gamatie","sequence":"additional","affiliation":[]},{"given":"P.","family":"Nouet","sequence":"additional","affiliation":[]},{"given":"F.","family":"Ouattara","sequence":"additional","affiliation":[]},{"given":"G.","family":"Sassatelli","sequence":"additional","affiliation":[]},{"given":"K.","family":"Jabeur","sequence":"additional","affiliation":[]},{"given":"P.","family":"Vanhauwaert","sequence":"additional","affiliation":[]},{"given":"A.","family":"Atitoaie","sequence":"additional","affiliation":[]},{"given":"I.","family":"Firastrau","sequence":"additional","affiliation":[]},{"given":"G.","family":"Di Pendina","sequence":"additional","affiliation":[]},{"given":"G.","family":"Prenat","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref3","first-page":"994","article-title":"NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory","volume":"31","author":"dong","year":"2012","journal-title":"TCAD"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927221"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref7","article-title":"MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory Technologies","author":"delobelle","year":"2017","journal-title":"Workshop on Emerging Memory Solutions — Technology Manufacturing Architectures DATE"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.154"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.1083"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342143.pdf?arnumber=8342143","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T18:11:23Z","timestamp":1525803083000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342143\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":7,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342143","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}