{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,28]],"date-time":"2026-07-28T14:26:45Z","timestamp":1785248805977,"version":"3.55.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342188","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T23:20:11Z","timestamp":1524525611000},"page":"1163-1166","source":"Crossref","is-referenced-by-count":21,"title":["Block convolution: Towards memory-efficient inference of large-scale CNNs on FPGA"],"prefix":"10.23919","author":[{"given":"Gang","family":"Li","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fanrong","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tianli","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jian","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783725"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062244"},{"key":"ref12","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2015","journal-title":"ICLRE"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1145\/2847263.2847265","article-title":"Going deeper with embedded fpga platform for convolutional neural network","author":"qiu","year":"2016","journal-title":"FPGA"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2964284.2967280"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021736"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1145\/2684746.2689060","article-title":"Optimizing fpga-based accelerator design for deep convolutional neural networks","author":"zhang","year":"2015","journal-title":"FPGA"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967011"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847276"},{"key":"ref2","article-title":"Learning both weights and connections for efficient neural networks","author":"han","year":"2015","journal-title":"NIPS"},{"key":"ref1","article-title":"Hardware-oriented approximation of convolutional neural networks","author":"gysel","year":"2016","journal-title":"ICLRE"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021727"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Dresden, Germany","start":{"date-parts":[[2018,3,19]]},"end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342188.pdf?arnumber=8342188","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,20]],"date-time":"2022-08-20T19:48:48Z","timestamp":1661024928000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342188\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":13,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342188","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}