{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,24]],"date-time":"2025-09-24T10:19:05Z","timestamp":1758709145807,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342189","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T23:20:11Z","timestamp":1524525611000},"page":"1167-1170","source":"Crossref","is-referenced-by-count":12,"title":["Examining the consequences of high-level synthesis optimizations on power side-channel"],"prefix":"10.23919","author":[{"given":"Lu","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Armaiti","family":"Ardeshiricham","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Tai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeremy","family":"Blackstone","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dejun","family":"Mu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryan","family":"Kastner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2014.7032504"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2006.40"},{"key":"ref10","first-page":"172","article-title":"An optimized s-box circuit architecture for low power aes design","author":"morioka","year":"2002","journal-title":"International Workshop on Cryptographic Hardware and Embedded Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ITCC.2004.1286711"},{"key":"ref11","first-page":"158","article-title":"A testing methodology for side-channel resistance validation","author":"goodwill","year":"2011","journal-title":"NIST Non-invasive Attack Testing Workshop"},{"key":"ref5","volume":"31","author":"mangard","year":"2007","journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0010-2"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-71039-4_8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_12"},{"key":"ref2","first-page":"918","article-title":"Adaptive Threshold Non-Pareto Elimination: Re-Thinking Machine Learning for System Level Design Space Exploration on FPGAs","author":"pingfan meng","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/11502760_28"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.83"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342189.pdf?arnumber=8342189","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T18:11:21Z","timestamp":1525803081000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342189\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":12,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342189","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}