{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:29:01Z","timestamp":1729621741098,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342197","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T23:20:11Z","timestamp":1524525611000},"page":"1199-1202","source":"Crossref","is-referenced-by-count":2,"title":["General floorplanning methodology for 3D ICs with an arbitrary bonding style"],"prefix":"10.23919","author":[{"given":"Jai-Ming","family":"Lin","sequence":"first","affiliation":[]},{"given":"Chien-Yu","family":"Huang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Routability-driven TSV-aware Floorplanning Methodology for Fixed-outline 3D ICs","author":"lin","year":"0","journal-title":"IEEE TCAD"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372645"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2050012"},{"key":"ref13","first-page":"725","article-title":"Temporal Floorplanning Using 3D-subTCG","author":"yuh","year":"2004","journal-title":"Proceedings of ASP-DAC"},{"year":"0","key":"ref14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593167"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2360453"},{"key":"ref6","first-page":"1808","article-title":"Planning Massive Interconnects in 3D Chips","volume":"34","author":"knechtel","year":"2015","journal-title":"IEEE TCAD"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846366"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2190537"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"526","DOI":"10.1145\/266021.266273","article-title":"Multilevel hypergraph partitioning: Application in VLSI domain","author":"karypis","year":"1997","journal-title":"Proceedings of DAC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2226584"},{"key":"ref1","first-page":"8","article-title":"The 3-D Interconnect Technology Landscape","author":"beyne","year":"2014","journal-title":"IEEE MDAT"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967071"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342197.pdf?arnumber=8342197","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,16]],"date-time":"2019-10-16T22:40:20Z","timestamp":1571265620000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342197\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":14,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342197","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}