{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T12:35:17Z","timestamp":1756384517835,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342237","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T23:20:11Z","timestamp":1524525611000},"page":"1435-1440","source":"Crossref","is-referenced-by-count":13,"title":["Technology-aware logic synthesis for ReRAM based in-memory computing"],"prefix":"10.23919","author":[{"given":"Debjyoti","family":"Bhattacharjee","sequence":"first","affiliation":[]},{"given":"Luca","family":"Amaru","sequence":"additional","affiliation":[]},{"given":"Anupam","family":"Chattopadhyay","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2009.5226356"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081665"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967020"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858298"},{"key":"ref14","first-page":"948","article-title":"Fast Logic Synthesis for RRAM-Based in-Memory Computing Using Majority-Inverter Graphs","author":"saeideh shirinzadeh","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2014.6968043"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2009.2028609"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"1092","DOI":"10.23919\/DATE.2017.7927152","article-title":"Endurance management for resistive logic-in-memory computing architectures","author":"shirinzadeh","year":"2017","journal-title":"2017 Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/23\/30\/305205"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865411"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/srep36652"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2017.04.010"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537020"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1021\/nl203687n"},{"key":"ref8","first-page":"1718","article-title":"Memristor based computation-in-memory architecture for data-intensive applications","author":"hamdioui","year":"2015","journal-title":"Proceedings of the 2015 Design Automation & Test in Europe Conference & Exhibition"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0970"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2017.10"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927095"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2015.2398217"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"journal-title":"The Art of Computer Programming Volume 4A Combinatorial Algorithms","year":"2011","author":"knuth","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/0012-365X(83)90173-5"},{"key":"ref24","article-title":"Majsynth: An n-input majority algebra based logic synthesis tool for quantum-dot cellular automata","author":"devadoss","year":"2015","journal-title":"Proc IWLS"},{"key":"ref23","first-page":"107","article-title":"A ternary operation in distributive lattices","author":"kiss","year":"1987","journal-title":"Selected Papers on Algebra and Topology by Garrett Birkhoff"},{"key":"ref26","first-page":"75","article-title":"Compatible majority decomposition","volume":"4","author":"varshavskii","year":"1968","journal-title":"Cybernetics and Systems Analysis"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488792"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2018,3,19]]},"location":"Dresden, Germany","end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342237.pdf?arnumber=8342237","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T18:32:47Z","timestamp":1525804367000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342237\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":26,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342237","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}