{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T09:19:44Z","timestamp":1790846384110,"version":"4.1.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.23919\/date.2018.8342276","type":"proceedings-article","created":{"date-parts":[[2018,4,23]],"date-time":"2018-04-23T19:20:11Z","timestamp":1524511211000},"page":"1634-1639","source":"Crossref","is-referenced-by-count":18,"title":["Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces"],"prefix":"10.23919","author":[{"given":"Maha","family":"Kooli","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Henri-Pierre","family":"Charles","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Clement","family":"Touzet","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bastien","family":"Giraud","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jean-Philippe","family":"Noel","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2016.2576903"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref12","author":"vahid","year":"2002","journal-title":"Embedded System Design A Unified Hardware\/Software Introduction"},{"key":"ref13","year":"1983","journal-title":"IEEE Standard Microcomputer System Bus"},{"key":"ref14","author":"null","year":"2014","journal-title":"The Essentials of Computer Organization and Architecture"},{"key":"ref15","year":"0","journal-title":"Mips32 Architecture"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844483"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090704"},{"key":"ref5","year":"0","journal-title":"UPMEM"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008501"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3130265.3130322"},{"key":"ref1","first-page":"1","article-title":"DRC 2: Dynamically Reconfigurable Computing Circuit based on memory architecture","author":"akyel","year":"2016","journal-title":"Rebooting Computing (ICRC) IEEE International Conference on"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"}],"event":{"name":"2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Dresden, Germany","start":{"date-parts":[[2018,3,19]]},"end":{"date-parts":[[2018,3,23]]}},"container-title":["2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8337149\/8341968\/08342276.pdf?arnumber=8342276","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T14:31:16Z","timestamp":1525789876000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8342276\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.23919\/date.2018.8342276","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}