{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:04:15Z","timestamp":1774631055548,"version":"3.50.1"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.23919\/date.2019.8714915","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T21:29:07Z","timestamp":1558042147000},"page":"1058-1063","source":"Crossref","is-referenced-by-count":3,"title":["Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators"],"prefix":"10.23919","author":[{"given":"Sheng","family":"Ma","sequence":"first","affiliation":[]},{"given":"Yang","family":"Guo","sequence":"additional","affiliation":[]},{"given":"Shenggang","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Libo","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Zhiying","family":"Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2847255"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.8"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.113"},{"key":"ref14","article-title":"Calculating Memory System Power For DDR3","year":"2007"},{"key":"ref15","article-title":"4Gb: ×4, ×8, ×16 DDR3 SDRAM","year":"2014"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.51"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1147\/rd.386.0673"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263591"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"14:1","DOI":"10.1145\/2764454","article-title":"BLIS: A Framework for Rapidly Instantiating BLAS Functionality","volume":"41","author":"van zee","year":"2015","journal-title":"ACM Trans Math Softw"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1356052.1356053"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"ref6","article-title":"TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor","year":"2014","journal-title":"Tech Rep"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2014.110"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2012.109"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628072"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.25"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0589"},{"key":"ref9","article-title":"Optimizing the Use of Static Buffers for DMA on a CELL Chip","author":"chen","year":"2006","journal-title":"LCPC"}],"event":{"name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Florence, Italy","start":{"date-parts":[[2019,3,25]]},"end":{"date-parts":[[2019,3,29]]}},"container-title":["2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8704855\/8714721\/08714915.pdf?arnumber=8714915","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,13]],"date-time":"2020-12-13T04:51:40Z","timestamp":1607835100000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8714915\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":19,"URL":"https:\/\/doi.org\/10.23919\/date.2019.8714915","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}