{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T22:52:46Z","timestamp":1774738366588,"version":"3.50.1"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.23919\/date.2019.8715004","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T21:29:07Z","timestamp":1558042147000},"page":"994-999","source":"Crossref","is-referenced-by-count":29,"title":["Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking"],"prefix":"10.23919","author":[{"given":"Mohammad Rahmani","family":"Fadiheh","sequence":"first","affiliation":[]},{"given":"Dominik","family":"Stoffel","sequence":"additional","affiliation":[]},{"given":"Clark","family":"Barrett","sequence":"additional","affiliation":[]},{"given":"Subhasish","family":"Mitra","sequence":"additional","affiliation":[]},{"given":"Wolfgang","family":"Kunz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337172"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3233\/JCS-2009-0393"},{"key":"ref12","first-page":"1","article-title":"ASLan++a formal security specification language for distributed spercystems","author":"von oheimb","year":"2010","journal-title":"Int Symposium on Formal Methods for Components and Objects"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2010.26"},{"key":"ref14","first-page":"337","article-title":"Verifying Information Flow Properties of Firmware Using Symbolic Execution","author":"pramod subramanyan","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref15","first-page":"313","article-title":"Formal verification of taint-propagation security properties in a commercial SoC design","author":"subramanyan","year":"2014","journal-title":"Proc of the Conference on Design Automation and Test in Europe (DATE)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2713393"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2017.11"},{"key":"ref18","article-title":"The rocket chip generator","author":"asanovic","year":"2016","journal-title":"EECS Department University of California Berkeley Tech Rep UCB\/EECS-2016-17"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.21236\/ADA360973"},{"key":"ref4","first-page":"22","article-title":"FLUSH+ RELOAD: a high resolution, low noise, L3 cache side-channel attack","volume":"1","author":"yarom","year":"2014","journal-title":"USENIX Security Symposium"},{"key":"ref3","article-title":"Cache missing for fun and profit","author":"percival","year":"2005","journal-title":"BSDCan"},{"key":"ref6","article-title":"Processor hardware security vulnerabilities and their detection by unique program execution checking","author":"fadiheh","year":"2018"},{"key":"ref5","article-title":"Reverse engineering intel DRAM addressing and exploitation","author":"pessl","year":"2015"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"109","DOI":"10.1145\/1508284.1508258","volume":"44","author":"tiwari","year":"2009","journal-title":"ACM SIGPLAN Notices"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1037187.1024404"},{"key":"ref2","article-title":"Meltdown","author":"lipp","year":"2018"},{"key":"ref1","article-title":"Spectre attacks: Exploiting speculative execution","author":"kocher","year":"2018"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.42"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006092"},{"key":"ref21","first-page":"55","article-title":"Symbolic quick error detection using symbolic initial state for pre-silicon verification","author":"fadiheh","year":"2018","journal-title":"Proc of the Conference on Design Automation and Test in Europe (DATE)"}],"event":{"name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Florence, Italy","start":{"date-parts":[[2019,3,25]]},"end":{"date-parts":[[2019,3,29]]}},"container-title":["2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8704855\/8714721\/08715004.pdf?arnumber=8715004","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T09:02:12Z","timestamp":1643274132000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8715004\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":21,"URL":"https:\/\/doi.org\/10.23919\/date.2019.8715004","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}