{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T15:41:40Z","timestamp":1725810100366},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.23919\/date.2019.8715021","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T21:29:07Z","timestamp":1558042147000},"page":"806-811","source":"Crossref","is-referenced-by-count":4,"title":["Towards Cross-Platform Inference on Edge Devices with Emerging Neuromorphic Architecture"],"prefix":"10.23919","author":[{"given":"Shangyu","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yi","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amelie Chi","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rui","family":"Mao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zili","family":"Shao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tao","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"2018","key":"ref10"},{"year":"2017","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2011.7477494"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3078633.3081032"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2968456.2968459"},{"key":"ref15","first-page":"265","article-title":"Tensorflow: A system for large-scale machine learning","author":"abadi","year":"2016","journal-title":"Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation (OSDI"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537907"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2693186"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2677442"},{"key":"ref8","first-page":"161","article-title":"Optimizing FPGA-based accelerator design for deep convolutional neural networks","author":"zhang","year":"2015","journal-title":"Proceedings of the 2015 ACM\/S1GDA International Symposium on Field-Programmable Gate Arrays (FPGA)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1755888.1755894"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.41"},{"year":"2018","key":"ref1","article-title":"GPU-based deep learning inference: A performance and power analysis"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541967"}],"event":{"name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2019,3,25]]},"location":"Florence, Italy","end":{"date-parts":[[2019,3,29]]}},"container-title":["2019 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8704855\/8714721\/08715021.pdf?arnumber=8715021","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,3]],"date-time":"2019-06-03T23:50:29Z","timestamp":1559605829000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8715021\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.23919\/date.2019.8715021","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}