{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:22:20Z","timestamp":1729617740563,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.23919\/date.2019.8715059","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T17:29:07Z","timestamp":1558027747000},"page":"444-449","source":"Crossref","is-referenced-by-count":1,"title":["Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis"],"prefix":"10.23919","author":[{"given":"Sourav","family":"Sanyal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Prabal","family":"Basu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aatreyi","family":"Bal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanghamitra","family":"Roy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koushik","family":"Chakraborty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"654","article-title":"VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches","author":"khatamifard","year":"2016","journal-title":"ICCD"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237021"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835937"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"515","DOI":"10.1145\/2749469.2750418","article-title":"CAWA: coordinated warp scheduling and cache prioritization for critical warp acceleration of GPGPU workloads","author":"lee","year":"2015","journal-title":"Proceedings of the 42Nd Annual International Symposium on Computer Architecture"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628107"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557150"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1773814.1773819"},{"journal-title":"NANGATE","year":"0","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2813379"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"ref4","first-page":"1","article-title":"Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking","author":"aguilera","year":"2014","journal-title":"2014 Design Automation and Test in Europe Conference and Exhibition"},{"journal-title":"AMD Accelated Parallel Processing (APP) Software Development Kit","year":"2016","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898100"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927140"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.71"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372564"},{"journal-title":"Near-Threshold Computing Reclaiming Moore's Law Through Energy Efficient Integrated Circuits","year":"2010","key":"ref2"},{"journal-title":"MIAOW GPU","year":"0","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2012.6263951"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/TSM.2007.913186","article-title":"VARIUS:A Model of Process Variation and Resulting Timing Errors for Microarchitects","volume":"21","author":"sarangi","year":"2008","journal-title":"IEEE Transactions on Semiconductor Manufacturing"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"}],"event":{"name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2019,3,25]]},"location":"Florence, Italy","end":{"date-parts":[[2019,3,29]]}},"container-title":["2019 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8704855\/8714721\/08715059.pdf?arnumber=8715059","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,12]],"date-time":"2020-12-12T23:52:05Z","timestamp":1607817125000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8715059\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":22,"URL":"https:\/\/doi.org\/10.23919\/date.2019.8715059","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}