{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:09:46Z","timestamp":1767262186036,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.23919\/date.2019.8715129","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T17:29:07Z","timestamp":1558027747000},"page":"1297-1300","source":"Crossref","is-referenced-by-count":11,"title":["Queue Based Memory Management Unit for Heterogeneous MPSoCs"],"prefix":"10.23919","author":[{"given":"Robert","family":"Wittig","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mattis","family":"Hasler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emil","family":"Matus","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gerhard","family":"Fettweis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591569"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176640"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024938"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CODES-ISSS.2013.6658992"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSoC.2012.6376362"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2360522"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3126535"},{"article-title":"Dhrystone Benchmark","year":"0","author":"longbottom","key":"ref17"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228568"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"ref6","article-title":"Epiphany-V: A 1024 processor 64-bit RISC System-On- Chip","volume":"abs 1610 0","author":"olofsson","year":"2016","journal-title":"CoRR"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2785799"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1145\/2742854.2747288","article-title":"Exploring multi-banked shared-L1 program cache on ultralow power, tightly coupled processor clusters","author":"loi","year":"2015","journal-title":"CF"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763085"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062188"},{"year":"2011","key":"ref1","article-title":"OMAR 4 mobile applications platform"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452013"}],"event":{"name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2019,3,25]]},"location":"Florence, Italy","end":{"date-parts":[[2019,3,29]]}},"container-title":["2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8704855\/8714721\/08715129.pdf?arnumber=8715129","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T21:03:28Z","timestamp":1643231008000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8715129\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":17,"URL":"https:\/\/doi.org\/10.23919\/date.2019.8715129","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}