{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,12]],"date-time":"2026-09-12T01:56:35Z","timestamp":1789178195165,"version":"build-2803163510"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.23919\/date.2019.8715289","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T17:29:07Z","timestamp":1558027747000},"page":"618-621","source":"Crossref","is-referenced-by-count":12,"title":["Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs"],"prefix":"10.23919","author":[{"given":"Aman","family":"Goel","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Karem","family":"Sakallah","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","article-title":"The Satisfiability Modulo Theories Library (SMT-LIB)","author":"barrett","year":"2016"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2481869"},{"key":"ref12","article-title":"Averroes 2","author":"goel","year":"0"},{"key":"ref13","article-title":"VCEGAR Verification Benchmarks","year":"0"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-49674-9_38"},{"key":"ref15","first-page":"1156","article-title":"Verilog2SMV: A Tool for Word-Level Verification","author":"ahmed irfan","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref16","article-title":"ABC: A system for sequential synthesis and verification","year":"2017"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2013.6679405"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-08867-9_22"},{"key":"ref19","article-title":"Yosys open synthesis suite","author":"wolf","year":"0"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-54862-8_4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/FMCAD.2017.8102233"},{"key":"ref6","article-title":"Enhancing PDR \/ IC3 with localization abstraction","author":"ho","year":"2017"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-08867-9_56"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2016.7886662"},{"key":"ref7","first-page":"173","article-title":"Lazy abstraction and sat-based reachability in hardware model checking","author":"vizel","year":"2012","journal-title":"FMCAD"},{"key":"ref2","first-page":"125","article-title":"Efficient implementation of property directed reachability","author":"een","year":"2011","journal-title":"FMCAD"},{"key":"ref1","first-page":"70","article-title":"Sat-based model checking without unrolling","author":"bradley","year":"2011","journal-title":"VMCAI"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/FMCAD.2017.8102251"},{"key":"ref20","year":"0"}],"event":{"name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Florence, Italy","start":{"date-parts":[[2019,3,25]]},"end":{"date-parts":[[2019,3,29]]}},"container-title":["2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8704855\/8714721\/08715289.pdf?arnumber=8715289","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,3]],"date-time":"2019-06-03T19:50:19Z","timestamp":1559591419000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8715289\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.23919\/date.2019.8715289","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}