{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,29]],"date-time":"2026-01-29T21:48:08Z","timestamp":1769723288492,"version":"3.49.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116193","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T23:28:37Z","timestamp":1592263717000},"page":"995-998","source":"Crossref","is-referenced-by-count":19,"title":["Towards Specification and Testing of RISC-V ISA Compliance<sup>\u22c6<\/sup>"],"prefix":"10.23919","author":[{"given":"Vladimir","family":"Herdt","sequence":"first","affiliation":[]},{"given":"Daniel","family":"Grose","sequence":"additional","affiliation":[]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775907"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19583-9_13"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1572272.1572303"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714912"},{"key":"ref14","article-title":"Formal verification of pulpino and other risc-v socs","year":"0"},{"key":"ref15","article-title":"GRIFT - galois RISC-V ISA formal tools","year":"0"},{"key":"ref16","article-title":"Spike RISC-V ISA simulator","year":"0"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FDL.2018.8524047"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317807"},{"key":"ref4","article-title":"RISC-V compliance task group","year":"0"},{"key":"ref3","article-title":"The challenge of RISC-V compliance","year":"0"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-10702-8_13"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1277900"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176425"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2002.1224444"},{"key":"ref2","author":"waterman","year":"2017","journal-title":"The RISC-V Instruction Set Manual Volume II Privileged Architecture"},{"key":"ref1","author":"waterman","year":"2017","journal-title":"The RISC-V instruction set manual volume i Unprivileged ISA"},{"key":"ref9","first-page":"1","article-title":"Rapid prototyping and compact testing of CPU emulators","author":"ma","year":"2010","journal-title":"RSP"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2020,3,9]]},"end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116193.pdf?arnumber=9116193","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,13]],"date-time":"2020-07-13T22:43:34Z","timestamp":1594680214000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116193\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":18,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116193","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}