{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T22:36:50Z","timestamp":1725662210745},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116253","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T23:28:37Z","timestamp":1592263717000},"page":"157-162","source":"Crossref","is-referenced-by-count":1,"title":["Tango: An Optimizing Compiler for Just-In-Time RTL Simulation"],"prefix":"10.23919","author":[{"given":"Blaise-Pascal","family":"Tine","sequence":"first","affiliation":[]},{"given":"Sudhakar","family":"Yalamanchili","sequence":"additional","affiliation":[]},{"given":"Hyesoon","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/PADS.2007.4"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105404"},{"key":"ref12","article-title":"A new distributed event-driven gate-level hdl simulation by accurate prediction","author":"kim","year":"0","journal-title":"DATE&#x2019;11"},{"article-title":"Verilator","year":"0","author":"snyder","key":"ref13"},{"key":"ref14","first-page":"1_","article-title":"Ieee standard for verilog hardware description language","year":"2006","journal-title":"IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.15514\/SYRCOSE-2007-1-2"},{"article-title":"Automatic and optimized generation of compiled high-speed rtl simulators","year":"2004","author":"alexey kupriyanov","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1269843.1269854"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.50"},{"journal-title":"VCS Industry Highest Performance Simulation Solution","year":"0","key":"ref8"},{"key":"ref7","first-page":"75","article-title":"systemc - a modeling platform supporting multiple design abstractions","author":"panda","year":"2001","journal-title":"International Symposium on System Synthesis (IEEE Cat No 01EX526) ISSS-01"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-27776-7_53"},{"journal-title":"Intelligent design of electronic assets (idea)","year":"2017","key":"ref1"},{"article-title":"Icarus verilog","year":"0","author":"williams","key":"ref9"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2020,3,9]]},"location":"Grenoble, France","end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116253.pdf?arnumber=9116253","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,6,16]],"date-time":"2020-06-16T03:58:29Z","timestamp":1592279909000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116253\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116253","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}