{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,13]],"date-time":"2025-12-13T06:52:13Z","timestamp":1765608733399,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116275","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T23:28:37Z","timestamp":1592263717000},"page":"364-369","source":"Crossref","is-referenced-by-count":11,"title":["Fast and Accurate DRAM Simulation: Can we Further Accelerate it?"],"prefix":"10.23919","author":[{"given":"Johannes","family":"Feldmann","sequence":"first","affiliation":[{"name":"Technische Universit\u00e4t Kaiserslautern,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"}]},{"given":"Kira","family":"Kraft","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Kaiserslautern,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"}]},{"given":"Lukas","family":"Steiner","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Kaiserslautern,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"}]},{"given":"Norbert","family":"Wehn","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Kaiserslautern,Microelectronic Systems Design Research Group,Kaiserslautern,Germany"}]},{"given":"Matthias","family":"Jung","sequence":"additional","affiliation":[{"name":"Fraunhofer IESE,Embedded Systems Division,Kaiserslautern,Germany"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"Ramulator: A Fast and Extensible DRAM Simulator","author":"kim","year":"2015","journal-title":"IEEE Computer Architecture Letters"},{"journal-title":"DrSim A Platform for Flexible DRAM System Research","year":"0","author":"jeong","key":"ref11"},{"journal-title":"Usimm the utah simulated memory module a simulation infrastructure for the jwac memory scheduling championship","year":"2012","author":"chatterjee","key":"ref12"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844484"},{"journal-title":"A Hybrid Analytical DRAM Performance Model","year":"2009","author":"yuan","key":"ref15"},{"key":"ref16","first-page":"1066","article-title":"Automated Construction of a Cycle-approximate Transaction Level Model of a Memory Controller","author":"todorov","year":"2012","journal-title":"Proceedings of the Design Automation & Test in Europe Conference DATE"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1090\/S0002-9904-1934-05988-3"},{"key":"ref18","first-page":"149","article-title":"Circuits and Trees in Oriented Linear Graphs","author":"aardenne-ehrenfest","year":"1987","journal-title":"Classic Papers in Combinatorics"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.8.63"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAMOS.2006.300818"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-27562-4_31"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2432516.2432521"},{"journal-title":"IEEE Standard for Standard SystemC Language Reference Manual","year":"2012","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3240302.3240322"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01724-7","author":"jacob","year":"2009","journal-title":"The Memory System You Can&#x2019;t Avoid It You Can&#x2019;t Ignore It You Can&#x2019;t Fake It"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2020,3,9]]},"location":"Grenoble, France","end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116275.pdf?arnumber=9116275","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,10,28]],"date-time":"2022-10-28T19:39:50Z","timestamp":1666985990000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116275\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":18,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116275","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}