{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T02:49:58Z","timestamp":1730342998746,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116304","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T23:28:37Z","timestamp":1592263717000},"page":"274-277","source":"Crossref","is-referenced-by-count":3,"title":["CMOS Implementation of Switching Lattices"],"prefix":"10.23919","author":[{"given":"Ismail","family":"Cevik","sequence":"first","affiliation":[]},{"given":"Levent","family":"Aksoy","sequence":"additional","affiliation":[]},{"given":"Mustafa","family":"Altun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715123"},{"journal-title":"Integrated circuit design International version A circuits and systems perspective","year":"2010","author":"weste","key":"ref11"},{"key":"ref12","article-title":"Logic synthesis and optimization benchmarks user guide: Version 3.0","author":"yang","year":"1991","journal-title":"MCNC Tech Rep"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"0","key":"ref13"},{"key":"ref4","first-page":"423","article-title":"Logic synthesis for switching lattices by decomposition with p-circuits","author":"bemasconi","year":"2016","journal-title":"DSD"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2015.51"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.05.004"},{"key":"ref5","first-page":"1","article-title":"Synthesis of switching lattices of dimensional-reducible boolean functions","author":"bemasconi","year":"2016","journal-title":"VLSI-SoC"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714809"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1016\/j.vlsi.2018.08.002","article-title":"Optimal and heuristic algorithms to synthesize lattices of four-terminal switches","volume":"64","author":"morgiil","year":"2019","journal-title":"Integration"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2661632"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.170"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-20323-8_7"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2020,3,9]]},"location":"Grenoble, France","end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116304.pdf?arnumber=9116304","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,13]],"date-time":"2020-07-13T22:43:03Z","timestamp":1594680183000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116304\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":13,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116304","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}