{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T14:18:53Z","timestamp":1772893133544,"version":"3.50.1"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116379","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T23:28:37Z","timestamp":1592263717000},"page":"732-737","source":"Crossref","is-referenced-by-count":14,"title":["Exact DAG-Aware Rewriting"],"prefix":"10.23919","author":[{"given":"Heinz","family":"Riener","sequence":"first","affiliation":[]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[]},{"given":"Mathias","family":"Soeken","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"SATbased exact synthesis: Encodings, topology families, and parallelism","author":"haaswijk","year":"2019","journal-title":"IEEE Trans on CAD of Integrated Circuits and Systems"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2014.2313451"},{"key":"ref12","article-title":"The EPFL logic synthesis libraries","author":"soeken","year":"2018","journal-title":"CoRR"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1996.563527"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref4","first-page":"51:1","article-title":"Efficient computation of ECO patch functions","author":"dao","year":"0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858328"},{"key":"ref6","article-title":"Scalable logic synthesis using a simple circuit structure","author":"mishchenko","year":"2006","journal-title":"Int’ I Workshop on Logic Synth"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317790"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317905"},{"key":"ref2","author":"de micheli","year":"1994","journal-title":"Synthesis and Optimization of Digital Circuits"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"198","DOI":"10.1109\/PGEC.1963.263531","article-title":"A catalog of three-variable Or-invert and Andinvert logical circuits","volume":"12","author":"hellerman","year":"1963","journal-title":"IEEE Trans Electronic Computers"},{"key":"ref9","first-page":"1649","article-title":"On-the-fly and DAG-aware: Rewriting Boolean networks with exact synthesis","author":"riener","year":"2019","journal-title":"Design Automation and Test in Europe"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2020,3,9]]},"end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116379.pdf?arnumber=9116379","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,13]],"date-time":"2020-07-13T22:43:07Z","timestamp":1594680187000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116379\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116379","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}