{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T15:03:00Z","timestamp":1780326180813,"version":"3.54.1"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116401","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T19:28:37Z","timestamp":1592249317000},"page":"696-701","source":"Crossref","is-referenced-by-count":15,"title":["Mixed-Signal Vector-by-Matrix Multiplier Circuits Based on 3D-NAND Memories for Neurocomputing"],"prefix":"10.23919","author":[{"given":"Mohammad","family":"Bavandpour","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shubham","family":"Sahay","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mohammad Reza","family":"Mahmoodi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dmitri","family":"Strukov","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2665781"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614659"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2901211"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1002\/cta.488"},{"key":"ref11","article-title":"Efficient mixed-signal neurocomputing via successive integration and re-scaling","author":"bavandpour","year":"2019","journal-title":"IEEE TVLSI"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2882194"},{"key":"ref8","article-title":"Silicon nanodisk array with a fin field-effect transistor for time-domain weighted sum calculation toward massively parallel spiking neural networks","volume":"9","author":"tohara","year":"2016","journal-title":"APEX"},{"key":"ref7","article-title":"A time-domain analog weighted- sum calculation model for extremely low power VLSI implementation of multi-layerneural networks","author":"wang","year":"2018"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1080\/23746149.2016.1259585"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2891688"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2020,3,9]]},"end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116401.pdf?arnumber=9116401","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,20]],"date-time":"2020-07-20T18:08:30Z","timestamp":1595268510000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116401\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":11,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116401","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}