{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T02:50:47Z","timestamp":1730343047990,"version":"3.28.0"},"reference-count":28,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116463","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T23:28:37Z","timestamp":1592263717000},"page":"939-944","source":"Crossref","is-referenced-by-count":2,"title":["Oracle-based Logic Locking Attacks: Protect the Oracle Not Only the Netlist"],"prefix":"10.23919","author":[{"given":"Emmanouil","family":"Kalligeros","sequence":"first","affiliation":[{"name":"University of the Aegean,Information & Comm. Systems Eng. Dept.,Samos,Greece"}]},{"given":"Nikolaos","family":"Karousos","sequence":"additional","affiliation":[{"name":"University of the Aegean,Information & Comm. Systems Eng. Dept.,Samos,Greece"}]},{"given":"Irene G.","family":"Karybali","sequence":"additional","affiliation":[{"name":"University of the Aegean,Information & Comm. Systems Eng. Dept.,Samos,Greece"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3060403.3060469"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951805"},{"key":"ref12","first-page":"189","article-title":"Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks","author":"xu","year":"2017","journal-title":"International Journal of Embedded Systems"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342086"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3060403.3060458"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203759"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3060403.3060492"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715163"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2019.2904838"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2404876"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"1048","DOI":"10.1109\/43.536711","article-title":"HOPE: An efficient parallel fault simulator for synchronous sequential circuits","volume":"15","author":"lee","year":"1996","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.193"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1007\/978-3-642-14295-6_5","article-title":"ABC: An academic industrial-strength verification tool","author":"brayton","year":"2010","journal-title":"Computer Aided Verification"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2511144"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2801220"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.284"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2017.2740364"},{"key":"ref1","article-title":"Defense-in-depth: A recipe for logic locking to prevail","author":"rahman","year":"2019","journal-title":"CoRR"},{"key":"ref20","article-title":"Logic locking for secure outsourced chip fabrication: A new attack and provably secure defense mechanism","author":"massad","year":"2017","journal-title":"CoRR"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196058"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2018.8607163"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0687"},{"journal-title":"CMOS VLSI Design A Circuits and Systems Perspective","year":"2011","author":"weste","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2017.8046226"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2018.8624866"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2020,3,9]]},"location":"Grenoble, France","end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116463.pdf?arnumber=9116463","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,2]],"date-time":"2022-08-02T23:48:08Z","timestamp":1659484088000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116463\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":28,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116463","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}