{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T04:52:40Z","timestamp":1725598360507},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116491","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T23:28:37Z","timestamp":1592263717000},"page":"999-1002","source":"Crossref","is-referenced-by-count":1,"title":["Post-Silicon Validation of the IBM POWER9 Processor"],"prefix":"10.23919","author":[{"given":"Tom","family":"Kolan","sequence":"first","affiliation":[{"name":"IBM Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hillel","family":"Mendelson","sequence":"additional","affiliation":[{"name":"IBM Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vitali","family":"Sokhin","sequence":"additional","affiliation":[{"name":"IBM Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"Reick","sequence":"additional","affiliation":[{"name":"IBM Systems & Technology Group"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elena","family":"Tsanko","sequence":"additional","affiliation":[{"name":"IBM Systems & Technology Group"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Greg","family":"Wetli","sequence":"additional","affiliation":[{"name":"IBM Systems & Technology Group"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024916"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-44953-1_53"},{"key":"ref6","article-title":"Reaching coverage closure in post-silicon validation","author":"adir","year":"2010","journal-title":"HVC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.898827"},{"key":"ref8","first-page":"146","article-title":"Advances in simultaneous multithreading testcase generation methods","author":"adir","year":"2010","journal-title":"HVC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26287-1_4"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.40"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062324"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-98116-1_17"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2020,3,9]]},"location":"Grenoble, France","end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116491.pdf?arnumber=9116491","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,2]],"date-time":"2022-08-02T23:48:03Z","timestamp":1659484083000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116491\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":9,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116491","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}