{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T02:51:04Z","timestamp":1730343064136,"version":"3.28.0"},"reference-count":27,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116525","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T23:28:37Z","timestamp":1592263717000},"page":"798-803","source":"Crossref","is-referenced-by-count":3,"title":["Synthesis of Fault-Tolerant Reconfigurable Scan Networks"],"prefix":"10.23919","author":[{"given":"Sebastian","family":"Brandhofer","sequence":"first","affiliation":[{"name":"University of Stuttgart,ITI,Stuttgart,Germany,D-70569"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael A.","family":"Kochte","sequence":"additional","affiliation":[{"name":"University of Stuttgart,ITI,Stuttgart,Germany,D-70569"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[{"name":"University of Stuttgart,ITI,Stuttgart,Germany,D-70569"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Survey of Scan Chain Diagnosis","volume":"25","author":"huang","year":"2008","journal-title":"IEEE Design & Test of Computers"},{"key":"ref11","first-page":"157","article-title":"Quick Scan Chain Diagnosis Using Signal Profiling","author":"yang","year":"2005","journal-title":"Int Conf on Computer Design (ICCD)"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/54.606001"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/VTS.2008.13"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/TEST.2000.894222"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/ATS.2015.7447934"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/ATS.2016.35"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/ATS.2017.34"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/IOLTS.2016.7604692"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/TEST.2012.6401555"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/SOCC.2016.7905437"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/DATE.2011.5763228"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/1837274.1837280"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/AUTEST.2018.8532559"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/IOLTS.2017.8046166"},{"key":"ref8","first-page":"268","article-title":"A Technique for Fault Diagnosis of Defects in Scan Chains","author":"guo","year":"2001","journal-title":"Proc IEEE Int Test Conf (ITC)"},{"key":"ref7","first-page":"91","article-title":"Device Selection for Failure Analysis of Chain Fails Using Diagnosis Driven Yield Analysis","author":"schuermyer","year":"2011","journal-title":"Proc Int Symp Testing Failure Anal (ISTFA)"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/MDAT.2017.2762903"},{"key":"ref9","first-page":"217","article-title":"Diagnosis of Scan Chain Failures","author":"wu","year":"1998","journal-title":"Proc IEEE Int&#x2019;l Symp on Defect and Fault Tolerance in VLSI Systems"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/MDAT.2017.2766604"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/ETS.2013.6569354"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/LATW.2016.7483366"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1145\/2699863"},{"key":"ref24","first-page":"317","article-title":"Symbolic Model Checking Using SAT Procedures Instead of BDDs","author":"biere","year":"1999","journal-title":"Proc Design Automation Conference (DAC)"},{"key":"ref23","article-title":"Reconfigurable Scan Networks: Formal Verification, Access Optimization, and Protection","author":"baranowski","year":"2014","journal-title":"Ph D Dissertation"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1016\/0166-218X(93)90086-4"},{"key":"ref25","article-title":"Synthesis of Robust Reconfigurable Scan Networks","author":"brandhofer","year":"2017","journal-title":"Master&#x2019;s thesis"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2020,3,9]]},"location":"Grenoble, France","end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116525.pdf?arnumber=9116525","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,2]],"date-time":"2022-08-02T23:47:45Z","timestamp":1659484065000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116525\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":27,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116525","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}