{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,3]],"date-time":"2026-04-03T06:59:14Z","timestamp":1775199554188,"version":"3.50.1"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116531","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T23:28:37Z","timestamp":1592263717000},"page":"298-301","source":"Crossref","is-referenced-by-count":4,"title":["Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities"],"prefix":"10.23919","author":[{"given":"Valentin","family":"Gherman","sequence":"first","affiliation":[]},{"given":"Samuel","family":"Evain","sequence":"additional","affiliation":[]},{"given":"Bastien","family":"Giraud","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref3","first-page":"125","article-title":"Enhancing the reliability of STT-RAM throught Circuit and System Level Techniques","author":"emre","year":"2012","journal-title":"IEEE Workshop on Signal Processing Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3240302.3240424"},{"key":"ref5","article-title":"Solid-state drive (SSD) requirements and endurance test method","author":"standard","year":"2011","journal-title":"JESD218"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1186\/1687-6180-2012-211"},{"key":"ref7","article-title":"Error control coding: fundamentals and applications","author":"lin","year":"1983"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/B978-1-55558-075-9.50019-3"},{"key":"ref1","first-page":"140","article-title":"Error analysis and retention-aware error management for nand flash memory","volume":"17","author":"cai","year":"2013","journal-title":"Intel Technology Journal"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2020,3,9]]},"end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116531.pdf?arnumber=9116531","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,13]],"date-time":"2020-07-13T22:42:37Z","timestamp":1594680157000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116531\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":8,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116531","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}