{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,6]],"date-time":"2026-02-06T00:49:44Z","timestamp":1770338984313,"version":"3.49.0"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116550","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T19:28:37Z","timestamp":1592249317000},"page":"1484-1489","source":"Crossref","is-referenced-by-count":12,"title":["STAIR: High Reliable STT-MRAM Aware Multi-Level I\/O Cache Architecture by Adaptive ECC Allocation"],"prefix":"10.23919","author":[{"given":"Mostafa","family":"Hadizadeh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elham","family":"Cheshmikhani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hossein","family":"Asadi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2904197"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2019.2923258"},{"key":"ref31","article-title":"REACT:Read\/Write Error Rate Aware Coding Technique for Emerging STT-MRAM Caches","volume":"55","author":"aliagha","year":"2019","journal-title":"IEEE Trans Mag (TMAG)"},{"key":"ref30","article-title":"STT-MRAM Scaling and Retention Failure","volume":"17","author":"naeimi","year":"2013","journal-title":"Intel Technology Journal (IATTJ)"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2495182"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2731959"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714946"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287686"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00056"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2875439"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2014.50"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/EDCC.2016.10"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2018.2888515"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2779151"},{"key":"ref28","article-title":"TSMC Corporation, Next generation MRAM","year":"0"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2018.2883745"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2928275.2928284"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2018.2796100"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.and.EUC.2013.63"},{"key":"ref29","article-title":"Solid-state magnetic memory","author":"corporation","year":"0"},{"key":"ref5","article-title":"Fast Miss Ratio Curve Modeling for Storage Cache","volume":"14","author":"hu","year":"2019","journal-title":"ACM Trans Storage (ToS)"},{"key":"ref8","first-page":"936","article-title":"An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture","author":"reza salkhordeh","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref7","article-title":"Hybrid Non-Volatile Disk Cache for Energy-efficient and High-performance Systems","volume":"18","author":"shi","year":"2013","journal-title":"ACM Trans Des Autom Electron Syst (TODAES)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2737832"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2455978"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2803302"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2019.00048"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3132402.3132416"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref24","article-title":"Storage Networking Industry Association, Microsoft enterprise traces","year":"0"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1416944.1416949"},{"key":"ref26","article-title":"Filebench: A Flexible Framework for File System Benchmarking","volume":"41","author":"tarasov","year":"2016","journal-title":"USENIX login"},{"key":"ref25","article-title":"HammerDB: The Open Source Oracle Load Test Tool","author":"shaw","year":"0"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2020,3,9]]},"end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116550.pdf?arnumber=9116550","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,13]],"date-time":"2020-07-13T18:43:32Z","timestamp":1594665812000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116550\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":34,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116550","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}