{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T15:49:36Z","timestamp":1774367376264,"version":"3.50.1"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.23919\/date48585.2020.9116553","type":"proceedings-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T19:28:37Z","timestamp":1592249317000},"page":"1133-1138","source":"Crossref","is-referenced-by-count":4,"title":["Floating Random Walk Based Capacitance Solver for VLSI Structures with Non-Stratified Dielectrics"],"prefix":"10.23919","author":[{"given":"Mingye","family":"Song","sequence":"first","affiliation":[]},{"given":"Ming","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Wenjian","family":"Yu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"SESS Rapid3D 20X Performance Improvement","author":"rollins","year":"2010"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2273985"},{"key":"ref12","article-title":"RWCap","year":"0"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(92)90332-7"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2224346"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2903011"},{"key":"ref16","article-title":"Polya Enumeration Theorem","author":"patotski","year":"2015"},{"key":"ref4","first-page":"835840","article-title":"Fast capacitance extraction in multilayer, conformal and embedded dielectric using hybrid boundary element method","author":"zhou","year":"2007","journal-title":"Proc DAC"},{"key":"ref3","article-title":"Raphael","year":"0"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2561968"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2440323"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2789730"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2782770"},{"key":"ref2","article-title":"Field-solver parasitic extraction goes main-stream","author":"dillinger","year":"2017"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-54298-5"},{"key":"ref9","article-title":"Decreasing parasitic capacitance in IC layouts","author":"kansal","year":"2014"}],"event":{"name":"2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2020,3,9]]},"end":{"date-parts":[[2020,3,13]]}},"container-title":["2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9112295\/9116186\/09116553.pdf?arnumber=9116553","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,13]],"date-time":"2020-07-13T18:42:29Z","timestamp":1594665749000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116553\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.23919\/date48585.2020.9116553","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}