{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,11,3]],"date-time":"2026-11-03T03:03:05Z","timestamp":1793674985719,"version":"4.5.1"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000185","name":"DARPA","doi-asserted-by":"publisher","award":["FA8750-17-1-0059"],"award-info":[{"award-number":["FA8750-17-1-0059"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9473910","type":"proceedings-article","created":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T18:11:46Z","timestamp":1629828706000},"page":"1186-1191","source":"Crossref","is-referenced-by-count":48,"title":["Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion"],"prefix":"10.23919","author":[{"given":"Prashanth","family":"Mohan","sequence":"first","affiliation":[{"name":"Carnegie Mellon University,Department of Electrical and Computer Engineering,Pittsburgh,PA,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Oguz","family":"Atli","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University,Department of Electrical and Computer Engineering,Pittsburgh,PA,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joseph","family":"Sweeney","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University,Department of Electrical and Computer Engineering,Pittsburgh,PA,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Kibar","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University,Department of Electrical and Computer Engineering,Pittsburgh,PA,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Larry","family":"Pileggi","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University,Department of Electrical and Computer Engineering,Pittsburgh,PA,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ken","family":"Mai","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University,Department of Electrical and Computer Engineering,Pittsburgh,PA,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"528","article-title":"Design obfuscation through selective post-fabrication transistor-level programming","author":"shihab","year":"0","journal-title":"2019 Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref11","author":"wolf","year":"0","journal-title":"Yosys Open SYnthesis Suite"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203759"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2019.8741035"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00103"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3319496"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2018.00080"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778002"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3317992"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2014.0028"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.24"},{"key":"ref9","author":"schiavone","year":"2020","journal-title":"Arnold an efpga-augmented risc-v soc for flexible and low-power iot end-nodes"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2021,2,1]]},"end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09473910.pdf?arnumber=9473910","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,26]],"date-time":"2025-08-26T19:11:26Z","timestamp":1756235486000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9473910\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":16,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9473910","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}