{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,10]],"date-time":"2026-05-10T10:15:08Z","timestamp":1778408108465,"version":"3.51.4"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9473925","type":"proceedings-article","created":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T22:11:46Z","timestamp":1629843106000},"page":"1152-1155","source":"Crossref","is-referenced-by-count":5,"title":["Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs"],"prefix":"10.23919","author":[{"given":"Maxim","family":"Mattheeuws","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bjorn","family":"Forsberg","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Kurth","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00029"},{"key":"ref3","article-title":"Evaluating Memory Subsystem of Configurable Heterogeneous MPSoC","author":"bansal","year":"0","journal-title":"Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT)"},{"key":"ref10","article-title":"LLVM: a Compilation Framework for Lifelong Program Analysis and Transformation","author":"lattner","year":"0","journal-title":"International Symposium on Code Generation and Optimization"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2011.33"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/InPar.2012.6339595"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3358183"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2017.8167755"},{"key":"ref8","article-title":"MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multi-Core Platforms","author":"yun","year":"0","journal-title":"IEEE Real-Time and Embedded Technology and Applications Symposium"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2980520"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"ref9","article-title":"AXI Traffic Generator v3.0 LogiCORE IP Product Guide","year":"2019","journal-title":"Xilinx"},{"key":"ref1","article-title":"Real-Time Systems - Design Principles for Distributed Embedded Applications","author":"kopetz","year":"1997","journal-title":"Real-Time Systems Series"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2021,2,1]]},"end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09473925.pdf?arnumber=9473925","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,29]],"date-time":"2022-01-29T00:02:43Z","timestamp":1643414563000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9473925\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":12,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9473925","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}