{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T02:19:11Z","timestamp":1771553951369,"version":"3.50.1"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9473992","type":"proceedings-article","created":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T22:11:46Z","timestamp":1629843106000},"page":"1-6","source":"Crossref","is-referenced-by-count":5,"title":["Storage Class Memory with Computing Row Buffer: A Design Space Exploration"],"prefix":"10.23919","author":[{"given":"Valentin","family":"Egloff","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Philippe","family":"Noel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maha","family":"Kooli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bastien","family":"Giraud","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lorenzo","family":"Ciampolini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roman","family":"Gauchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cesar","family":"Fuguet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric","family":"Guthmuller","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mathieu","family":"Moreau","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Michel","family":"Portal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2015.7314400"},{"key":"ref11","article-title":"Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing","author":"noel","year":"2020","journal-title":"DATE"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2966484"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3370748.3406550"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2912941"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2019.8920373"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176872"},{"key":"ref18","article-title":"NVSim: A Circuit-Level Performance, Energy, and Area Model for Ernerging Nonvolatile Memory","author":"dong","year":"2012","journal-title":"TCADICS"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3219617.3219661"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3317979"},{"key":"ref6","year":"2020","journal-title":"UPMEM"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref8","article-title":"1 Mb 0.41 µm2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing","author":"li","year":"2014","journal-title":"JSSC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS45951.2020.9128340"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.42"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268468"},{"key":"ref20","doi-asserted-by":"crossref","DOI":"10.1145\/1064978.1065034","article-title":"Pin: building customized program analysis tools with dynamic instrumentation","author":"luk","year":"2005","journal-title":"SIGPLAN Not"},{"key":"ref22","author":"pouchet","year":"2012","journal-title":"PolyBench The Polyhedral Benchmark Suite"},{"key":"ref21","article-title":"Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces","author":"kooli","year":"2018","journal-title":"DATE"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2021,2,1]]},"end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09473992.pdf?arnumber=9473992","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,28]],"date-time":"2022-01-28T23:38:01Z","timestamp":1643413081000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9473992\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":22,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9473992","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}